1. Field of the Invention
The present invention relates to the field of integrated circuit chips, particularly the protection of integrated circuit chips from electrostatic discharges.
2. Background of the Invention
Integrated circuits for radio frequency (RF) applications require both active and passive elements. Active elements include metal-oxide-silicon field-effect-transistors (MOSFETs) and bipolar transistors. In RF CMOS (complimentary-metal-oxide-silicon), active elements include N-channel MOSFETs and P-channel MOSFETs. In RF silicon BiCMOS (bipolar-CMOS) technology, active elements include silicon bipolar junction transistors (BJT) in addition to CMOS MOSFETs. In silicon germanium (SiGe) technology, active elements include hetro-junction bipolar transistors (HBT.) For RF circuits both passive and active elements are needed. Examples of passive elements include resistors, capacitors and inductors. In RF applications, passive elements having a high quality factor (Q) are required. High Q capacitors have minimal resistive effects. High Q resistors have low parasitic capacitance. High quality inductors have low series resistance and minimal capacitive coupling to the chip substrate.
Typically, high Q passive resistors, capacitors and inductors are placed away from the semiconductor substrate. Inductors, especially, are placed above the chip interconnect metallurgy to minimize capacitive and inductive coupling to the semiconductor substrate. Inductors are formed from the same materials and processes as used to form the interconnect metallurgy. When a circuit using inductors is required, thick interlevel insulating films and deep vias are used. However, as CMOS interconnect metallurgy scales (linewidth and line thickness decrease) inductor-substrate distance decreases, degrading the Q of the inductor.
Additionally, electrostatic discharge (ESD) is a phenomenon known to degrade or destroy discrete devices such as transistors, diodes, inductors, capacitors and resistors in integrated circuits. Both voltage and current spikes can break down the dielectric or doped regions in various portions of individual semiconductor devices, thus rending the entire device or even the entire chip completely or partially inoperable.
Capacitive loading becomes a major concern for integrated circuits running at radio frequencies (RF), i.e. greater than one GHz, as the capacitive loading of conventional ESD devices has an adverse effect on device performance. Conventional ESD devices are large area transistors or diodes fabricated in the semiconductor substrate of the integrated circuit. The capacitance looking into an integrated circuit is given by:CTOT=CCKT+CESD  (1)
where: CTOT is the total capacitance of the device;
CCKT is the capacitance of the integrated circuit; and
CESD is the capacitance of the ESD protection device.
RF circuits are designed with low CCKT values, but ESD protection circuits and devices have relatively high CESD values and the value of CTOT can become dominated by the value of CESD. For example, at one GHz, a CTOT of one pF or less is acceptable. At 10 GHz, CTOT must be about 0.1 pF or less, which is difficult to achieve with conventional ESD protection circuits. At 100 GHz, CTOT must be about 0.01 pF or less, which is very difficult if possible to achieve with conventional ESD protection circuits. ESD protection elements are needed for both active and passive elements.
Field emission devices (FEDs)and spark gaps provide ESD protection with little or no added capacitance, but are difficult to implement on semiconductor chips and pose potential contamination and therefore reliability problems. For integrated circuits operating in the RF regime, a method of providing ESD protection is that does not create a reliability problem is needed.
Therefore, a solution is needed to the problem of providing high Q resistors, capacitors and inductors as CMOS scales smaller as well as a solution to the related problem of providing ESD protection for both the active and passive (especially high Q) elements of RF circuits.